In article <2729d477-5467-4ff6-a399-0fbc2607c3c5@s12g2000prg.googlegroups.com>, tsu <sujithreddy.t@gmail.com> wrote: >I am getting compilation error in VCS with the following piece of >verilog code >module A(...) Try this: I think the inside of the for needs to be a named block. The block name ends up in the net list. >genvar i; >generate > for(i=0;i<depth;i++) begin : foo > assign storage_data[(((i+1)*width)-1):(width*i)]=ram_array[i]; end >endgenerate -- /* jhallen@world.std.com AB1GO */ /* Joseph H. Allen */ int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0) +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2 ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}