On 2007-11-20, japonetz@gmail.com <japonetz@gmail.com> wrote: > Hello, > Is it possible to define in Verilog that the sinulator (Modelsim) will > show the Enumerated Type and not value, i.e., in satates example, will > show st1, st2, sr3... instead of 0,1,2 .... > I know that the solution for this is to create virtual function in > Modelsim, but it's highly inconvenient. > I wonder if there is a trick to do it straight forward. Hi, defining your own virtual functions is quite annoying. However, I have a small TCL script that can help you on my homepage: http://www.da.isy.liu.se/~ehliar/stuff/ Look for stateenumerate.tcl and you will find the script and some images of how it works. I have tested it in ModelSim 6.2g but I don't know if it works in later versions of Modelsim. If it doesn't, let me know and I can take a look at it to see if it is easy to fix. /Andreas