Some minor additions, <mjl296@hotmail.com> wrote in message news:1192192606.728998.203260@q5g2000prf.googlegroups.com... > On 11 Oct, 21:30, e2po...@yahoo.com wrote: >> i've started using verilog around 6 months back and used it to design ..snip > > On a budget, you may find it difficult to find a simulator that > supports SystemVerilog, or mixed simulation of SystemC with Verilog - > other members of the group may be able to suggest free/cheap tools > that support this. I personally have used ModelSim, Questa and VCS for > this task, but none are cheap. > > In theory it is possible to write SystemC at the RTL level, and you > could simulate this with any C++ compiler. However, you won't find a > synthesis tool that accepts it, so it is of little use. There are a number of SystemC synthesis tools available ranging from the low'ish cost SystemCrafters up to $$$ ForteDS. There is also a SystemC Synthesis standard draft. Hans www.ht-lab.com > > On balance, I suspect that if you don't have the budget for the big > guns, then you are probably best using some mix of C modelling and > vanilla Verilog to test your device. > > I hope this is of some help. > > Mark

<e2point@yahoo.com> wrote in message news:1192274801.669362.39770@q3g2000prf.googlegroups.com... > >The excitement about SystemVerilog and SystemC is justified. Both >>languages give you powerful features for behavioural modelling, and >>SystemVerilog adds lots of powerful random test generation constructs >>and functional coverage constructs. > > one last question > what is i start learning vhdl instead? how does vhdl compare with > systemverilog? > There's a newsgroup comp.lang.vhdl that may help.