Group: comp.lang.verilog


Subject: Usage of $input
From: John_H
Date: 10/3/2007 3:04:47 PM
"kb33" <kanchan.devarakonda@gmail.com> wrote in message news:1191446366.756948.31550@22g2000hsm.googlegroups.com... > > Putting it more simply, lets say you have the following instructions > in your testbench (I am skipping the definitions of the various > signals..) > > > initial > begin > //Initialization.... > > sys_clk <= 0; > reset_n <= 0; > sig_a <= 1; > sig_b <= 0; > > #(2*period) > reset_n <= 1; > > #(55*period); > begin > sig_a <= 8; > sig_b <= 10; > end > > #(1*period) > sig_a <= 4; > > #(100*period) $finish; > end > > Usually, you would just have these statements in your testbench. But > if you do not want these statements in your testbench, but instead > want to put them in another text file that your testbench can open and > read using a system task or function, how would you do that? If > possible, I want to do it without any Tcl commands or anything outside > of my testbench. That is the reason I inquired about the usage of the > $input command (from inside the testbench). > > Kanchan How about 'include "myInitFile.v"