Group: comp.lang.verilog


Subject: 30khz from 1Mhz
From: Mike Lewis
Date: 9/27/2007 4:46:10 PM
<trescot@gmail.com> wrote in message news:1190923488.283062.295530@w3g2000hsg.googlegroups.com... > Hi guys, > > I have a design question. > Any idea how can I generate a 32 kHZ clock from 1Mhz clock source ? It > doesn't have to be exactly accurate. > > > Thanks > >\ A divide by 31 counter design gets close ... how close do you need to be? Mike