"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1190135851.404698.228480@y42g2000hsy.googlegroups.com... > Hi, > 1. I am talking about GUESSING the largest number of state machines a > current finished design may have. Not ceiling. My official guess: light blue.

>"A synchronous or an asynchronous reset signal is vital, either with >clear routing or a hidden procedure within other initial procedures." Nonsense. Consider self synchronizing scramblers. They are just a batch of XOR gates and FFs. From any unspecified state, they will put out garbage for N clock ticks. After that, the output is determined by the input. -- These are my opinions, not necessarily my employer's. I hate spam.

>Can you please put more information on scramblers and their state >machines? >I don't know scramblers. The idea is to generate a random bit stream that you can XOR with a data stream for a serial link to make sure there are no long strings of 0s or 1s. It's a pile of FFs and XORs. The same logic as CRCs. LFSR, Linear Feedback Shift Register is another buzzword. The "self synchronizing" part means that the output doesn't need to be reset. It will get to a known state after N cycles. A single bit error on the link will produce a multi-bit error after the descrambler. That pattern of bits is the polynomial used by the scrambler. The wiki article is pretty good. http://en.wikipedia.org/wiki/Scrambler_(randomizer) A digital communications text might be better. -- These are my opinions, not necessarily my employer's. I hate spam.

Far too restrictive. In a TDMA architecture I implemented, one RAM contains 512 locations of N bits each: 512 individual state machines. Each 'virtual process' was identical, but had different inputs. For this particular design, a lower bound on the number of states would be 4*512 = 2048, since I had four instances of that particular module. Probably double that, due to similar logic structures downstream. If it were appropriate for the application, scale it up appropriately. Depending on required processing speed, state machine complexity, target device capabilities, etc., an internal (or external) RAM could contain thousands -- or millions -- of individal state machines. For my particular case, the next states were defined by equations, the last states were the outputs of the RAMs, and the particular state machine was selected by the RAMs address. (I instantiated the RAMs, but they could have been generated by a process. However, the tools aren't always that good at properly inferring dual-port RAMs, so if you need a particular structure... ) So, what are the limiting factors? Available logic, available storage (registers and memory), creativity, and objectives. What is the value of the answer? JTW "Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1190052227.791942.311570@w3g2000hsg.googlegroups.com... > Hi, > OK, a state machine is defined by standard one process or two > processes in VHDL. > > There is no short cut. > > It can be implemented in anywhere in a design and where the state > machine is located is decided by compilers and beyond the interest of > this topics. > > I have to expand the guess to include Verilog group people, because > VHDL people may have no chance to do the designs. > > I may know the answer. The final result may surprise everyone who > gives a guess. > > Thank you. > > Weng >

>Scramble technology still uses randomized serial and XOR now? After 8b/ >10b technology, I think other randomized XOR scramble technology is >dying out, is it right? 8b/10b has a 20% bandwidth hit. That may be reasonable on short links where the cost of the link is small relative to the cost of the end points. But change hats from a computer room to a Telco. Their costs are mostly the fibers in the ground. Using scramblers is a no-brainer for 20% cost reduction. -- These are my opinions, not necessarily my employer's. I hate spam.

>Hi Hal, >Scrambler cannot be counted as a state machine in any sense. Why not? It has inputs, outputs, and internal state. Sure looks like a state machine to me. >The most important factor for a circuit counted as a state machine is >that its states are mutually exclusive and only one state is active in >any cycle. Which part of that does a scrambler not meet? Remember, I'm talking about a LFSR type scrambler running in bit serial mode, not a n 8b/10b encoder. >Shift registers can be counted as a state machine only when only one >bit is set or reset among all its bits. Otherwise it cannot be counted >as a state machine. Huh? A shift register seems like an even simpler example of a state machine that doesn't need a reset to do useful work. I'm thinking of a simple serial-in, serial-out shift register, a delay line. It's "state" is the last N bits shifted in. If I was explaining a shift register or scrambler to somebody, I probably wouldn't start by calling it a state machine and drawing the classic picture of states and transitions, but it might be handy to use tricks from state machine theory, like if it has N bits of internal state (aka FFs) it can only have 2^N distinct states. -- These are my opinions, not necessarily my employer's. I hate spam.

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:8qydnY9KVevHXW_bnZ2dnUVZ_gednZ2d@comcast.com... > John_H wrote: > (snip) > >> 80B/10B is not a scrambler. It's a coding mechanism used to balance the >> DC offset of the encoded stream. It's a straight encode/decode. > > You could say it that way, but if you need a modulation method > for clock recovery it can be used in place of a scrambler and > simpler modulation method. > > Modulation is used for different reasons: > > 1) Clock recovery > 2a) Band limited channel > 2b) AC coupled system > > Considering those, 8B/10B is not so different from a scrambler. > > -- glen It's not "so" different, but the advantages of each are different. The items that strike me the most are that 8B/10B provides better DC balance and scramblers provide a smoother spread of power across a wider bandwidth.

>A.2: Depending on the complexity of the design, as many as required, >provided that each FSM do not exceed more than 15 states or so...(more >than 15, becomes harder to debug, and follow..) >A.3. Embedded in A.2, hence, max 15-20 states per FSM would be a best >suit based on my experience...Larger than 20, the FSM should be broken >down into 2 FSMs... It's perfectly reasonable to build FSMs with hundreds or even thousands of states. The trick is to think of it as software and build yourself an assembler so you can really implement it that way. People have been using ROMs for this type of state machine for a long time. 256x8 ROMs were common back in the old TTL/DIP days. That style of FSMs usually has clumps of states that don't branch. If you draw the typical circles and arrows state diagram, you might want to include each clump in one circle. It just takes several cycles/states to do the "action" associated with a state transition. -- These are my opinions, not necessarily my employer's. I hate spam.

>For a 4-bit shift register to be counted as a state machine, it must >have data: >"0001", "0010", "0100" and "1000" for an active high state machine, or >"1110", "1101", "1011" and "0111" for an active low state machine. That's total nonsense. Your pattern describes a one-hot state machine. That simplifies decoding states, but there is nothing in the rules of state machines that says I have to use that encoding. It's common to encode states in kludgy ways that make decoding convenient. -- These are my opinions, not necessarily my employer's. I hate spam.