"Neo" <zingafriend@yahoo.com> wrote in message news:1190127000.066671.307080@q5g2000prf.googlegroups.com... > > Actually t_ready is input from outside so I don't control it. Guess, > the only way out is to do it in on neg phase of pclk as you said. > > Neo You're not answering the questions and you may be completely missing the point here. If you ARE in a simulation environment, that "external" t_ready needs to work with the "external" pclk. If you AREN'T in a simulation environment, you have timing issues with the hold time for t_ready relative to pclk. It's rarely a good thing to use the negedge of a clock though the use certainly has its place. The negedge I suggested was for simulation control so that visually (and for any inter-domain clock issues) you have an OBVIOUS difference between your stimulus and the internal signals.