Hi A question for the Verilog-AMS language lawyers out there (if there are any). Here's the scenario. 10ns simulation, analog code contains $timer(0.0, period) <code> Initially, period is 1.0, but at 5ns, it changes to 2.0. When should the next timer event occur? Should it continue from 5ns, and thus occur at 7ns (then 9ns), or should it occur as if the timer had been running from 0ns with a period of 2.0, and occur at 6ns (then 8 and 10ns). A bientot Paul