Group: comp.arch.fpga

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Spartan3E Slave Serial Daisy chain  (1 messages)
Structured way of changing eg time constants for real world build / simulation?  (5 messages)
bidirectional in fpga  (1 messages)
implementing MAC protocols on fpga  (1 messages)
Students: where to go for help  (1 messages)
Xilinx Encrypted bit file  (2 messages)
Block-ram FIFO in Xilinx  (4 messages)
FPGA for hobby use  (6 messages)
Xilinx Virtex-II Newbie  (3 messages)
synopsys translate_off  (1 messages)
V4FX: Cannot access EMAC1 of Dual MAC system  (2 messages)
TI DSP soft core in Xilinx?  (4 messages)
Lattice Semi  (3 messages)
jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers  (2 messages)
VHDL language is out of date! Why? I will explain.  (5 messages)
New Laptop for work  (2 messages)
Quartus II warning: "pass-through logic has been added"  (6 messages)
Low cost FPGA w/serdes  (2 messages)
synthesizing vqm with parameters with quartus 7.1sp1  (1 messages)
Altera webpack for Linux?  (1 messages)
Parallel to Serial ASI ...  (2 messages)
TPS75003 Spartan-3(E) Regulator Design  (1 messages)
Coolrunner in system programming - XAPP0058 - viable?  (1 messages)
FPGA Editor (9.2.03i) under Linux x86_64  (3 messages)
Measuring setup and hold time in Lab  (3 messages)
Unable to scan device chain  (4 messages)
DDR2 dqs pin // virtex4  (3 messages)
DCM with instable clock  (1 messages)
Virtex 5 PCB Designers Guide: required capacitors  (1 messages)
How to simulate these example CORDIC code?  (4 messages)
Fifo Block-RAM Xilinx ISE - port empty  (1 messages)
Converting a ByteBlasterMV into a ByteBlaster II?  (3 messages)
PCI Mezzanine Card with Xilinx Virtex-II  (1 messages)
Hook open drain "power good" to nSTATUS or nCONFIG?  (1 messages)
Start-up Xilkernel on Microblaze  (1 messages)
xilinx spartan 3 + 16 adc  (2 messages)
yet another Altera Cyclone II EP2C35 dev. board  (1 messages)
using fpga as programmable connection  (1 messages)
DDR2 controler  (1 messages)
Gnd plane coupling with DDR routing from FPGA <-> DDR?  (26 messages)
Behavioral Simulation working but Post-route Simulation is not.  (1 messages)
What tools do you use ? Why ?  (1 messages)
I/O short circuit protection?  (1 messages)
What's the difference for VHDL code between simulation and synthesis?  (8 messages)
Hand solder that FPGA on your prototype  (4 messages)
lossless compression in hardware: what to do in case of uncompressibility?  (1 messages)
Global Reset using Global Buffer  (1 messages)
Pipelining of FPGA code  (2 messages)
Christmas and New Year at Enterpoint  (1 messages)
Traffic Light with counter  (3 messages)
MI5 Persecution: How to Identify the Persecutors (2004)  (1 messages)
Using SRAM Memory CY7C1386C  (2 messages)
Using DDR RAM on XUP V2Pro board  (1 messages)
can't genarate block memory cores in ISE 7.1i  (2 messages)
R: can't genarate block memory cores in ISE 7.1i  (1 messages)
lossless compression in hardware: what to do in case of uncompressibility?  (1 messages)
lossless compression in hardware: what to do in case of uncompressibility?  (1 messages)
Virtex5: LVCMOS33 and LVDS_25 inputs (with DIFF_TERM) in same bank?  (2 messages)
calculation of clock cycle /instructions...  (1 messages)
clock cycle per Instructions  (1 messages)
"simultaneously switching output"  (2 messages)
BUFGCE  (1 messages)
can't install Centos 5.1 x86_64 and Xilinx ISE 9.2 evaluation  (1 messages)
why do i see negative clock hold time  (1 messages)
Drigmorn1 - The Cheapest FPGA Development Board???  (1 messages)
converting verilog to vhdl  (2 messages)
student requiring assistance :)  (1 messages)
For God's sake !! It did not work at all !!!  (1 messages)
How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?  (1 messages)
Which FPGA and memory to use? The eternal X vs. A question.  (5 messages)
DDS generator with interpolated samples for Spartan3E development board  (2 messages)
Questions about Timing closure Floorplan and individual timing constraints  (1 messages)
Xilinx ise 9.2i clean up project files  (1 messages)
GAL16V8  (1 messages)
sobel in vhdl  (1 messages)
Poor quality Xilinx boards ? Your experience ?  (5 messages)
Initializing Micron DDR2 Memory  (1 messages)
Poor quality Xilinx boards ? Your experience ?  (4 messages)
Debugging designs that are running on FPGA  (1 messages)
spartan 3e VQ100 serious question  (2 messages)
Newbee Microblaze system BRAM utlization confusion  (1 messages)
Spartan 3E starter kit expansion boards - Gb ethernet & video  (1 messages)
Xilinx Dual processor design  (1 messages)
serial ATA question  (2 messages)
sampling error between 2 clocks  (5 messages)
global clock (gclk) input at xilinx virtex4 fpga  (1 messages)
What timing constraint value should be set for input/output module?  (1 messages)
Ethernet data rates using Spartan-3 FPGA  (1 messages)
Call For Papers: WORLDCOMP'08: Computer Science & Computer Engineering Conferences, USA, July 2008  (1 messages)
multidimensional arrays in VHDL?  (2 messages)
Tarfessock1 - FPGA Cardbus Development Board  (1 messages)
Xilinx's ML505  (1 messages)
Xilinx DCM outputs for DDR  (1 messages)
ASIC verification job info request  (4 messages)
help with rising edge matching  (2 messages)
Can't get Quartus to Infer Dual Port Ram for Stratix2GX  (1 messages)
What is  (1 messages)
Routing Vccint on four-layer PCB  (2 messages)
Xilinx Spartan 3 JTAG issues  (1 messages)
PowerPC & Spartan-3E Embedded Processing Development Kit - SP3E1600E MicroBlaze Edition  (2 messages)


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